Interleaved clocks may suffer from clock phase mismatch, especially as the output frequency increases towards the Nyquist frequency. Thus, there is a need to address this clock phase mismatch in order to insure performance at high frequency.
Possible approaches to solving this clock phase mismatch include using a dedicated circuit block such as a high-speed phase detector or using an injection locking oscillator. However, the inclusion of a high-speed phase detector as a dedicated circuit block adds extra loading on the highest speed clock path for phase correction. In particular, loading can become very high if wide skew correction range is necessary. Such high loading can lead to degradation of clock quality. Also, clock skew correction interrupts the synchronization loop and makes the calibration process complicated if a phase-interpolator is used for the correction block. In addition, the inclusion of a high-speed phase detector adds extra loading on the highest speed clock path for phase detection.
Still further, a high-speed phase detector may have limited performance due to limited bandwidth or offset. Typically, increasing device size in order to reduce offset inflates loading. A conventional current phase detection circuit's sensitivity is limited. Also, the conventional detection circuit typically requires an inductor which consumes a large area.
The alternative solution of using an injection locking oscillator also has several disadvantages. Using an injection locking oscillator may only work for a very narrow frequency range. The rise-time/fall-time of the injection locking oscillator may have large variations over different frequencies. The injection locking oscillator also requires many stages to effectively cancel input clock mismatch. The duty cycle error of a clock may not be corrected and may sometimes increase. Further, the injection locking oscillator involves a difficult circuit layout that easily creates high systematic phase offset.
Furthermore, clock phase itself is difficult to control, and may involve adding a dedicated circuit.
The present disclosure provides solutions to one or more of the above-noted problems in conventional interleaved data converters.